Diode logic elements or, and. Diode gates or, and Logic 2

LOGIC ELEMENTS

General information.

It was noted above that logical functions and their arguments take the value of log.0 and log.1. In this case, it should be borne in mind that in devices log.0 and log.1 corresponds to a voltage of a certain level (or form). The most commonly used two ways of physical representation of log.0 and log.1: potential and impulse.

With a potential form (Fig. 2.1, a and 2.1, b), a voltage of two levels is used to represent log.0 and log.1: a high level corresponds to log.1 ( level log.1) and the low level corresponds to log.0 ( level log.0). This way of representing the values ​​of logical quantities is called positive logic. Relatively rarely, the so-called negative logic is used, in which log.1 is assigned a low voltage level, and log.0 is a high level. In what follows, unless otherwise stated, we will use only positive logic.

With an impulse form, log.1 corresponds to the presence of an impulse, logical 0 - the absence of an impulse (Fig. 2.1, c).

Note that if, with a potential form, the information corresponding to the signal (log.1 or log.0) can be determined at almost any moment of time, then with an impulse form, the correspondence between the voltage level and the value of the logical value is established at certain discrete points in time (the so-called clock points in time), indicated in Fig. 2.1, in integer numbers t = 0, 1, 2, ...

General designations of logical elements.




Logical elements of basis AND, OR, NOT on discrete components.

diode element OR (assembly)

The logic element OR, performed on diodes, has two or more inputs and one output. The element can work with both potential and impulse representation of logical values.

On fig. 2.2,a shows a diagram of a diode element for working with potentials and pulses of positive polarity. When using negative logic and negative potentials, or pulses of negative polarity, it is necessary to change the polarity of the diodes, as shown in Figure 2.2, b.

Consider the operation of the circuit in Fig. 2.2a. If a pulse (or high potential) acts on only one input, then the diode connected to this input opens and the pulse (or high potential) is transmitted through the open diode to the resistor R. In this case, a voltage is formed on the resistor R of the polarity at which the diodes in the circuits of the remaining inputs are under the action of the blocking voltage.

rice. 2.2.

If signals corresponding to log.1 are simultaneously received at several inputs, then with strict equality of the levels of these signals, all diodes connected to these inputs will open.

If the resistance of the open diode is small compared to the resistance of the resistor R, the output voltage level will be close to the input signal level, regardless of how many inputs simultaneously have a log.1 signal.

Note that if the levels of the input signals differ, then only the diode of that input opens, the signal level of which has the highest value. A voltage is generated across the resistor R, close to the largest of the voltages acting on the inputs. All other diodes are closed, disconnecting sources with a low signal level from the output.

Thus, at the output of the element, a signal corresponding to log.1 is formed, if at least one of the inputs has a log.1. Therefore, the element implements the disjunction operation (OR operation).

Consider the factors that affect the shape of the output pulse. Let the element have n inputs and one of them is supplied with a rectangular voltage pulse from a source with an output impedance Rout. The diode connected to this input is open and presents a low resistance. The remote diodes are closed, the capacitances C d of their p-n - transitions through the output resistances of the sources connected to the inputs turn out to be connected in parallel to the output of the element. Together with the load and installation capacitance C n, some equivalent capacitance C eq \u003d C d + (n-1) C d is formed, connected in parallel R (Fig. 2.3, a).

At the moment the pulse is applied to the input, due to the capacitance C ek, the output voltage cannot increase abruptly; it grows exponentially with the time constant

(because R out< R), стремясь к значению U вх R/(R + R вых).

rice. 2.3.

At the end of the input pulse, the voltage across the charged capacitor C eq cannot drop abruptly; it decreases exponentially with time constant (at this time, all diodes are closed); because the duration of the cutoff of the output pulse is greater than the duration of its front (Fig. 2.3, b). The supply of the next pulse to the input of the element is allowed only after the residual voltage at the output from the action of the previous pulse has decreased to a certain small value. Therefore, the slow decline in the output voltage causes the need to increase the clock interval and, therefore, is the reason for the decrease in performance.

diode element AND (coincidence circuit)

The AND gate has one output and two or more inputs. Diode element And can work with information presented both in potential and in impulse form.

Figure 2.4, a shows the circuit used for positive input voltages. When using negative logic and negative input voltages, or pulses of negative polarity, it is necessary to change the polarity of the power supply voltage and the polarity of the diodes (Fig. 2.4, b).

rice. 2.4.

Let one of the inputs of the circuit in Fig. 2.4, a have a low voltage level corresponding to the level of log.0. The current will be closed in the circuit from the source E through the resistor R, an open diode and a low input voltage source. Since the resistance of an open diode is small, a low potential from the input through an open diode will be transmitted to the output. Diodes connected to the remaining inputs, which are affected by a high voltage level, turn out to be closed. The voltage acting on the diode can be determined by summing the voltages when bypassing the circuit external to the diode from its anode to the cathode. With such a bypass, the voltage across the diode turns out to be equal to U d \u003d U out - U in. Thus, the output voltage applied to the anodes of the diodes is positive for them, tending to open the diodes; the input voltage applied to the cathode is negative, tending to close the diode. And if u are out< u вх, то U д отрицательно и диод закрыт. Именно поэтому, когда на выходе элемента низкий потенциал (уровень лог.0), а на входе высокий потенциал (уровень лог.1), подключенный к этому входу диод оказывается закрытым.

Thus, if at least one of the inputs has a low-level voltage (log.0), then a low-level voltage (log.0) is formed at the output of the element.

Let high-level voltages (log.1) act on all inputs. They may differ slightly in meaning. This will open the diode that is connected to the input with a lower voltage. This voltage through the diode will be transmitted to the output. The remaining diodes will be practically closed. The output will be set to a high level voltage (log.1).

Therefore, at the output of the element, the voltage of the log.1 level is set if and only if the voltage of the log.1 level is applied at all inputs. Thus, we make sure that the element performs a logical AND operation.

Consider the shape of the output pulse (Figure 2.5).

We will assume that some equivalent capacitive element C eq is connected to the output, the capacitance of which includes the capacitances of the load, mounting and closed diodes. At the moment a voltage pulse is applied simultaneously to all inputs, the voltage at C eq (at the output of the element) cannot increase abruptly. All diodes are initially closed input voltages, which are negative for diodes. Therefore, the input sources will be disconnected from the C eq. Capacitor C eq is charged from source E through resistor R. The voltage across the capacitor (and hence at the output of the element) grows exponentially with a time constant (Fig. 2.5, b). At the moment when u out exceeds the minimum of the input voltages, the corresponding diode will open and the growth of u in will stop. The current from source E, previously closed through C eq, switches to an open diode circuit.


rice. 2.5.

At the end of the input pulses, all diodes open with a positive voltage for them u out. There is a relatively fast discharge C eq through open diodes and low output resistances of the input signal sources. The output voltage decreases exponentially with a small time constant .

Comparison of the forms of the output pulses of the diode elements OR and AND shows that in the OR element, the pulse cutoff is more extended, in the AND element - its front.

transistor element NOT (inverter)

rice. 2.6.

The NOT operation can be implemented by the key element shown in Fig. 2.6a. Note that this element performs a NOT operation only in the potential form of representing boolean values. When the input signal is low, corresponding to log.0, the transistor is closed, a high level voltage E (log1) is set at its output. And vice versa, at a high input voltage level (log.1 level), the transistor is saturated, a voltage close to zero (log.0 level) is set at its output. Graphs of input and output voltages are shown in fig. 2.6b.

Integral logical elements of the basis AND-NOT and their parameters.

Integral logic elements are used in the potential form of representation of logical values.

The circuit of the integrated element AND-NOT of the DTL type is shown in fig. 2.7. The element can be divided into two consecutive functional parts. The input values ​​are applied to the part that is a diode AND gate. The second part of the element, made on a transistor, is an inverter (performing a NOT operation). Thus, the logical AND and NOT operations are sequentially performed in the element, and, therefore, in general, it implements the logical AND-NOT operation.

If a high-level voltage (log.1) acts at all inputs of the element, then a high-level voltage is formed at the output of the first part of the circuit (at point A). This voltage is transmitted through the diodes VD to the input of the transistor, which is in saturation mode, at the output of the element, the voltage is low (log.0).

rice. 2.7.

If at least one of the inputs will have a low-level voltage (log.0), then a low-level voltage (close to zero) is formed at point A, the transistor is closed and a high-level voltage is generated at the output of the element (log.1). The operation of the diode element AND in the integrated version differs from the operation of the same element discussed above on discrete components in that when log.1 is simultaneously applied to all inputs, all diodes turn out to be closed. Due to this, the current consumption from the source that supplies the input voltage log.1 is reduced to a very small value.

Let us consider in more detail the operation of the inverter part of the element. First, we note some features of integrated circuit transistors. The microcircuits use silicon transistors of the n-p-n type (in this case, the collector supply voltage has a positive polarity and the transistor opens with a positive voltage between the base and the emitter). On fig. Figure 2.8 shows a typical collector current versus voltage between base and emitter in active mode. The peculiarity of this characteristic is that the transistor practically begins to open at relatively high values ​​​​of the base voltage (usually exceeding 0.6 V). This feature makes it possible to do without sources of base bias, since even with positive base voltages of tenths of a volt, the transistor turns out to be practically closed. Finally, another feature of the microcircuit transistor is that the voltage between the collector and emitter in saturation mode is relatively high (it can be 0.4 V and higher).

rice. 2.8.

Let the signals to the inputs of a logical element be fed from the outputs of similar elements. Let's take the log.1 voltage equal to 2.6 V, the log.0 voltage equal to 0.6 V, the voltages on the open diodes and the base-emitter voltage of the saturated transistor equal to 0.8 V.

When a voltage of 2.6 V (log.1 level) is applied to all inputs (see Fig. 2.7), the diodes at the inputs are closed, the current from the source E 1 through the resistor R 1, the diodes VD passes into the base of the transistor, setting the transistor to saturation mode. At the output of the element, a low-level voltage of 0.6 V is formed (log.0 level). The voltage U A is equal to the sum of the voltages on the diodes VD and the voltage U BE: 3 0.8 \u003d 2.4 V. Thus, the input diodes are under a reverse voltage of 0.2 V.

If at least one of the inputs is supplied with a low level voltage of 0.6 V (log.0 level), then the current from the source E 1 is closed through the resistor R 1 , an open input diode and the input signal source. In this case, U A \u003d 0.8 + 0.6 \u003d 1.4 V. At this voltage, the transistor turns out to be closed due to the bias provided by the VD diodes (these diodes are called bias diodes). The current from the source E 1, flowing through the resistor R 1, diodes VD and resistor R 2, creates a voltage drop close to U A on the bias diodes. The voltage U BE is positive, but much less than 0.6 V, and the transistor is closed.

Element AND-NOT diode-transistor logic (DTL)

The main circuit of the element shown in Fig. 2.9, as well as the circuit of the DTL element considered above, consists of two functional parts connected in series: a circuit that performs the AND operation and an inverter circuit. A distinctive feature of the construction of the AND circuit in the TTL element is that it uses one multi-emitter transistor MT, which replaces the group of input diodes of the DTL circuit. The MT emitter junctions act as input diodes, and the collector junction plays the role of a biasing diode in the transistor base circuit of the inverting part of the element circuit.

When considering the principle of operation of the MT, it can be represented as consisting of separate transistors with combined bases and collectors, as shown in Fig. 2.9, b.


rice. 2.9

Let the voltage level log.1 (3.2 V) be applied to all inputs of the element. The possible distribution of potentials at individual points of the circuit is shown in Fig. 2.10, a. The MT emitter junctions turn out to be reverse-biased (the emitter potentials are higher than the base potentials), the MT collector junction, on the contrary, is forward-biased (the collector potential is lower than the base potential). Thus, MT can be represented by transistors operating in the active mode with inverse connection (in such an inclusion, the emitter and collector change roles). A multi-emitter transistor is designed in such a way that its gain in inverse switching is much less than unity. Therefore, the emitters take a small current from the input signal sources (in contrast to the DTL elements, where this current through closed input diodes is practically zero). The base current MT flows through the collector junction into the base of the transistor VT, keeping the latter in saturation mode. The output is set to a low level voltage (log.0).


rice. 2.10.

Consider another state of the circuit. Let at least one of the inputs have a voltage level log.0. The resulting distribution of potentials is shown in Fig. 2.10, b. The MT base potential is higher than the emitter and collector potential. Therefore, both emitter and collector junctions are forward biased and the MT is in saturation mode. The entire base current MT is closed through emitter junctions. The voltage between the emitter and the collector is close to zero, and the low voltage level acting on the emitter is transmitted through the MT to the base of the transistor VT. The transistor VT is closed, the output is a high voltage level (log.1 level). In this case, almost the entire base current of the MT is closed through the forward-biased emitter junction of the MT.

Basic parameters of integral logic elements

Consider the main parameters and ways to improve them.

Input Pooling Factor defines the number of element inputs to supply boolean variables. An element with a large input pooling factor has more logical possibilities.

load capacity (or output fanout) determines the number of inputs of similar elements that can be connected to the output of this element. The higher the load capacity of the elements, the less the number of elements may be required when building a digital device.

To increase the load capacity in DTL and TTL, a complicated scheme of the inverting part is used. An element diagram with one of the options for a complex inverter is shown in Fig. 2.11.


rice. 2.11

Figure 2.11a illustrates the enabled element mode. If a log.1 level voltage is applied at all inputs, the entire current flowing through the resistor R1 is supplied to the base of the transistor VT2. Transistor VT2 opens and goes into saturation mode. The emitter current of transistor VT2 flows into the base of transistor VT5, keeping this transistor open. Transistors VT3 and VT4 are closed, since at the emitter junction of each of them a voltage of 0.3V operates, which is insufficient to open the transistors.

On fig. 2.11b shows the mode of the switched off element. If at least one of the inputs has a log.0 level voltage, then the current of the resistor R1 is completely switched to the input circuit. Transistors VT2 and VT5 are closed, the output voltage level is log.1. Transistors VT3, VT4 operate in two series-connected emitter followers, the input of which is supplied with current through the resistor R2, and the emitter current of the VT4 transistor feeds the load.

In the off state of the element with a simple inverter, the current is supplied to the load from the power source through the collector resistor Rk with a large resistance (see Fig. 2.11, b). This resistor limits the maximum value of the current in the load (with an increase in the load current, the voltage drop across Rk increases, the output voltage decreases). In an element with a complex inverter, the emitter current of the VT4 transistor operating in the emitter follower circuit is supplied to the load. Since the output resistance of the emitter follower is small, the output voltage is weaker than the envy of the load current, and large values ​​of the load current are permissible.

Performancelogical elements is one of the most important parameters of logical elements, it is estimated by the signal propagation delay from the input to the output of the element.

Figure 2.12 shows the form of the input and output signals of the logic element (inverter): t 1,0 3 - the delay time of switching the output of the element from state 1 to state 0; t 0.1 3 - switching delay from state 0 to state 1. As can be seen from the figure, the delay time is measured at a level average between log.0 and log.1 levels. Average signal propagation delay t s cf = 0.5 (t 0.1 3 + t 1.0 3). This parameter is used in calculating the signal propagation delay in complex logic circuits.

rice. 2.12

Let's consider the factors influencing the performance of a logical element and methods for improving performance.

To increase the switching speed of transistors in the element, it is necessary to use higher-frequency transistors and switching transistors to produce large control currents in the base circuit; a significant reduction in the delay time is achieved through the use of a saturated mode of operation of the transitors (in this case, the time required for the absorption of minor carriers in the base when the transistors are turned off is excluded).

rice. 2.13

This process can be accelerated by the following methods:

· a decrease in R (and hence a decrease in the time constant ); however, at the same time, the current and power consumed from the power source increase;

· use of small voltage drops in the element;

· the use of an emitter follower at the output of the element, which reduces the effect of the load capacitance.

Below, when describing the logical elements of emitter-coupled logic, the use of these methods to increase the speed of the elements is shown.

rice. 2.13

Noise immunity is determined by the maximum value of the interference that does not cause disruption of the element.

To quantify the noise immunity, we use the so-called transfer characteristic logic element (inverter). Figure 2.14 shows a typical form of this characteristic.

rice. 2.14

The transfer characteristic is the dependence of the output voltage on the input. To obtain it, it is necessary to connect all the inputs of the logic element and, by changing the voltage at the output, note the corresponding voltage values ​​at the output.

When the input voltage increases from zero to the threshold level log.0 U 0 p the output voltage decreases from the level log.1 U 1 min . A further increase in the input leads to a sharp decrease in the output. At large values ​​of the input voltage, exceeding the threshold level log.1 U 0 max . Thus, during normal operation of the element in a static (steady) mode, input voltages U 0 p< u вх

Permissible are such interferences that, superimposed on the input voltage, will not bring it into the region of unacceptable values ​​U 0 p< u вх

Emitter-coupled logic gate

A typical diagram of an integrated element of emitter-coupled logic is shown in fig. 2.15.


rice. 2.15.

Transistors VT 0, VT 1, VT 2, VT 3 work in the current switch circuit, transistors VT 4, VT 5 - in the output emitter followers. The diagram shows the values ​​of the potentials at various points when a voltage of log.1 level is applied to the input; the values ​​of the potentials of the same points are enclosed in brackets for the case when voltages of the log.0 level are applied to all inputs of the element. The values ​​of these potentials correspond to the following levels:

· power supply voltage E to = 5 V;

· level log.1 U 1 = 4.3 V;

· level log.1 U 0 = 3.5 V;

· the voltage between the base and the emitter of an open transistor U be \u003d 0.7 V.

Let's consider the principle of operation of the ESL integral logic element (see Fig. 2.15).

Let voltage U 1 = 4.3 V be applied to Vx 1. Transistor VT 1 is open; the emitter current of this transistor creates a voltage drop across the resistor R U a = U 1 -U be = 4.3 - 0.7 = 3.6 V; the collector current creates a voltage U Rk1 = 0.8 V on the resistor R k1; voltage at the collector of the transistor U b \u003d E k - U Rk1 \u003d 5 - 0.8 \u003d 4.2 V.

The voltage between the base and emitter of the transistor VT 0 U be VT0 \u003d U - U a \u003d 3.9 - 3.6 \u003d 0.3 V; this voltage is not enough to open the transistor VT 0. Thus, the open state of any of the transistors VT 1 , VT 2 , VT 3 leads to the closed state of the transistor VT 0 . The current through the resistor R k2 is very small (only the base current of the transistor VT 5 flows) and the voltage on the collector VT 0.

Consider another state of the logic element. Let the voltage log.0 U 0 \u003d 3.5 V operate at all inputs. In this case, the transistor VT 0 turns out to be open (of all the transistors whose emitters are combined, the one on the basis of which a higher voltage opens); U a \u003d U - U be \u003d 3.9 - 0.7 \u003d 3.2 V; the voltage between the base and emitter of transistors VT 1, VT 2, VT 3 is equal to U be VT1 ... VT0 \u003d U 0 - U a \u003d 3.5 - 0.7 \u003d 0.3 V and these transistors are closed; U b = 5 V; U in \u003d 4.2 V.

Voltages from points b and c are transmitted to the outputs of the element through emitter repeaters; in this case, the voltage level decreases by the value U be \u003d 0.7 V. Let us pay attention to the important circumstance that the voltages at the outputs are equal to U 1 (4.3 V) or U 0 (3.5 V).

Let's find out what logical function is formed at the outputs of the element.

At the point in and at Out 2, a low-level voltage is formed when the transistor VT 0 is open, i.e. in the case when x 1 \u003d 0, x 2 \u003d 0, x 3 \u003d 0. For any other combination of values ​​​​of input variables, the transistor VT 0 is closed and a high level voltage is generated at Output 2. It follows from this that a disjunction of variables x 1 Vx 1 Vx 1 is formed on the output 2 . At Out 1, the OR-NOT function is formed.

Therefore, the logical element performs the OR-NOT and OR operations.

In ESL microcircuits, point d is made common, and point d is connected to a power source with a voltage of -5V. In this case, the potentials of all points of the circuit are reduced to 5 V.

The considered logical element belongs to the class of the fastest elements (short signal propagation delay time) is provided by the following factors: open transistors are in active mode (not in saturation mode); the use of emitter followers at the outputs accelerates the process of recharging the capacitances connected to the outputs; transistors are connected according to the switching circuit with a common base, which improves the frequency properties of transistors and speeds up the process of their switching; a small difference in logical levels U 1 -U 0 = 0.8 V is selected (however, this leads to a relatively low noise immunity of the element).

Logic elements on MIS transistors

rice. 2.16

On fig. 2.16 shows a diagram of a logic element with an induced channel of type n (the so-called n MIS technology). The main transistors VT 1 and VT 2 are connected in series, the transistor VT 3 acts as a load. In the case when a high voltage U 1 acts on both inputs of the element (x 1 \u003d 1, x 2 \u003d 1), both transistors VT 1 and VT 2 turn out to be open and a low voltage U 0 is set at the output. In all other cases, at least one of the transistors VT 1 or VT 2 is closed and the voltage U 1 is set at the output. Thus, the element performs a logical NAND function.

rice. 2.17

On fig. 2.17 shows a diagram of an OR-NOT element. A low voltage U 0 is set at its output, if at least one of the inputs has a high voltage U 1, which opens one of the main transistors VT 1 and VT 2.

rice. 2.18

Shown in fig. 2.18 the circuit is a circuit of the OR-NOT element of the CMOS technology. In it, transistors VT 1 and VT 2 are the main ones, transistors VT 3 and VT 4 are load ones. Let the high voltage be U 1 . In this case, the transistor VT 2 is open, the transistor VT 4 is closed, and regardless of the voltage level at the other input and the state of the remaining transistors, a low voltage U 0 is set at the output. The element implements a logical OR-NOT operation.

The CMTD circuit is characterized by a very low current consumption (and, consequently, power) from power sources.

Logic elements of integral injection logic

rice. 2.19

On fig. 2.19 shows the topology of the logic element of the integral injection logic (I 2 L). To create such a structure, two phases of diffusion in silicon with n-type conductivity are required: during the first phase, regions p 1 and p 2 are formed, the second phase - regions n 2 .

The element has the structure p 1 -n 1 -p 2 -n 1 . It is convenient to consider such a four-layer structure, representing it as a connection of two conventional three-layer transistor structures:

p 1 - n 1 - p 2 n 1 - p 2 - n 1

The scheme corresponding to such a representation is shown in Fig. 2.20, a. Consider the operation of the element according to this scheme.

rice. 2.20

Transistor VT 2 with a structure of the type n 1 -p 2 -n 1 performs the functions of an inverter with several outputs (each collector forms a separate output of the element according to the open collector circuit).

Transistor VT 2, called injector, has a structure like p 1 -n 1 -p 2 . Since the area n 1 for these transistors is common, the emitter of the transistor VT 2 must be connected to the base of the transistor VT 1; the presence of a common area p 2 leads to the need to connect the base of the transistor VT 2 with the collector of the transistor VT 1 . This is how the connection of transistors VT 1 and VT 2 is formed, shown in Fig. 2.20, a.

Since a positive potential acts on the emitter of the transistor VT 1, and the base is at zero potential, the emitter junction is forward-biased and the transistor is open.

The collector current of this transistor can close either through the transistor VT 3 (inverter of the previous element), or through the emitter junction of the transistor VT 2.

If the previous logical element is in the open state (transistor VT 3 is open), then at the input of this element a low voltage level, which, acting on the basis of VT 2, keeps this transistor in the closed state. The current of the injector VT 1 closes through the transistor VT 3. When the previous logic element is closed (transistor VT 3 is closed), the collector current of the injector VT 1 flows into the base of the transistor VT 2, and this transistor is set to the open state.

Thus, when VT 3 is closed, the transistor VT 2 is open and, conversely, when VT 3 is open, the transistor VT 2 is closed. The open state of the element corresponds to the state log.0, the closed state corresponds to the state log.1.

The injector is a constant current source (which may be common to a group of elements). Often use the conditional graphic designation of the element, shown in Fig. 2.21b.

On fig. 2.21a shows a circuit that implements the OR-NOT operation. The connection of the collectors of elements corresponds to the operation of the so-called mounting AND. Indeed, it is enough that at least one of the elements is in the open state (log.0 state), then the injector current of the next element will be closed through the open inverter and a low level of log.0 will be set at the combined output of the elements. Therefore, at this output, a value corresponding to the logical expression x 1 x 2 is formed. Applying the de Morgan transform to it leads to the expression x 1 x 2 = . Therefore, this connection of elements really implements the OR-NOT operation.


rice. 2.21

Logical elements AND 2 L have the following advantages:

· provide a high degree of integration; in the manufacture of I 2 L circuits, the same technological processes are used as in the manufacture of integrated circuits on bipolar transistors, but the number of technological operations and the necessary photomasks is less;

· low voltage is used (about 1V);

· provide the possibility of exchanging power for speed over a wide range (you can change the power consumption by several orders of magnitude, which will accordingly lead to a change in speed);

· are in good agreement with TTL elements.

On fig. 2.21b shows the transition scheme from the elements AND 2 L to the TTL element.

In digital circuitry, a digital signal is a signal that can take on two values, considered as a logical "1" and a logical "0".

Logic circuits are implemented on logical elements: "NOT", "AND", "OR", "AND-NOT", "OR-NOT", "XOR" and "Equivalence". The first three logical elements allow you to implement any arbitrarily complex logical function in a boolean basis. We will solve problems for logic circuits implemented in the Boolean basis.

Several standards are used to designate logic elements. The most common are American (ANSI), European (DIN), international (IEC) and Russian (GOST). The figure below shows the designations of logical elements in these standards (to enlarge, you can click on the picture with the left mouse button).

In this lesson, we will solve problems for logic circuits, in which logic elements are designated in the GOST standard.

Tasks for logic circuits are of two types: the problem of synthesizing logic circuits and the problem of analyzing logic circuits. We will start with the second type of problem, since in this order it is possible to quickly learn how to read logic diagrams.

Most often, in connection with the construction of logical circuits, the functions of the algebra of logic are considered:

  • three variables (to be considered in the problems of analysis and in one problem of synthesis);
  • four variables (in synthesis problems, that is, in the last two paragraphs).

Consider the construction (synthesis) of logical circuits

  • in the boolean basis "AND", "OR", "NOT" (in the penultimate paragraph);
  • in the also common bases "AND-NOT" and "OR-NOT" (in the last paragraph).

The task of analyzing logic circuits

The task of analysis is to determine the function f implemented by a given logic circuit. When solving such a problem, it is convenient to follow the following sequence of actions.

  1. The logical scheme is divided into tiers. Tiers are assigned sequential numbers.
  2. The outputs of each logical element are indicated by the name of the desired function, provided with a digital index, where the first digit is the tier number, and the remaining digits are the ordinal number of the element in the tier.
  3. For each element, an analytical expression is written that relates its output function to the input variables. The expression is defined by the logical function implemented by the given logical element.
  4. Substitution of some output functions through others is performed until a Boolean function is obtained, expressed through input variables.

Example 1

Solution. We divide the logic circuit into tiers, which is already shown in the figure. Let's write down all the functions, starting from the 1st tier:

x, y, z :

x y z f
1 1 1 0 1 1 1 1
1 1 0 0 0 0 1 0
1 0 1 0 0 0 1 0
1 0 0 0 0 0 1 0
0 1 1 0 0 0 1 0
0 1 0 0 0 0 1 0
0 0 1 0 0 0 1 0
0 0 0 1 0 1 0 0

Example 2 Find the boolean function of the logic circuit and make a truth table for the logic circuit.

Example 3 Find the boolean function of the logic circuit and make a truth table for the logic circuit.


We continue to search for the boolean function of the logic circuit together

Example 4 Find the boolean function of the logic circuit and make a truth table for the logic circuit.

Solution. We break the logic circuit into tiers. Let's write down all the functions, starting from the 1st tier:

Now let's write all the functions, substituting the input variables x, y, z :

As a result, we get the function that the logic circuit implements at the output:

.

Truth table for a given logic circuit:

x y z f
1 1 1 0 1 1
1 1 0 0 1 1
1 0 1 1 0 1
1 0 0 0 0 0
0 1 1 0 1 1
0 1 0 0 1 1
0 0 1 0 1 1
0 0 0 0 1 1

Example 5 Find the boolean function of the logic circuit and make a truth table for the logic circuit.

Solution. We break the logic circuit into tiers. The structure of this logic circuit, unlike the previous examples, has 5 tiers, not 4. But one input variable - the lowest one - runs through all the tiers and directly enters the logic element in the first tier. Let's write down all the functions, starting from the 1st tier:

Now let's write all the functions, substituting the input variables x, y, z :

As a result, we get the function that the logic circuit implements at the output:

.

Truth table for a given logic circuit:

x y z f
1 1 1 1 1 1
1 1 0 1 1 1
1 0 1 1 0 1
1 0 0 1 0 1
0 1 1 1 1 1
0 1 0 1 1 1
0 0 1 1 0 1
0 0 0 1 0 1

The problem of synthesizing logic circuits in a Boolean basis

The development of a logical circuit according to its analytical description is called the problem of synthesis of a logical circuit.

Each disjunction (logical sum) corresponds to the "OR" element, the number of inputs of which is determined by the number of variables in the disjunction. Each conjunction (logical product) corresponds to the "AND" element, the number of inputs of which is determined by the number of variables in the conjunction. Each negation (inversion) corresponds to the element "NOT".

Often the design of a logic circuit begins with the definition of a logic function that the logic circuit must implement. In this case, only the truth table of the logic circuit is given. We will analyze just such an example, that is, we will solve a problem that is completely inverse to the problem of analyzing logic circuits considered above.

Example 6 Construct a logic circuit that implements a function with a given truth table:

x y f
1 1 0
1 0 0
0 1 1
0 0 0

Solution. We analyze the truth table for the logic circuit. We define a function that will be obtained at the output of the circuit and intermediate functions that take arguments at the input x And y. In the first line, the result of the implementation of the output function, given that the values ​​of the input variables are equal to one, should be a logical "0", in the second line - with different values ​​of the input variables, the output should also be a logical "0". Therefore, it is necessary that the output function be a conjunction (logical product).

Just like standard Boolean expressions, information at the inputs and outputs of various logic elements or logic circuits can be collected in a single table - a truth table.

truth table gives a visual representation of the system of logical functions. The truth table displays the signals at the outputs of logic elements for all possible combinations of signals at their inputs.

As an example, consider a logic circuit with two inputs and one output. Let's mark the input signals as "A" and "B", and the output as "Q". There are four (2²) possible combinations of input signals that can be applied to these two inputs ("ON - signal present" and "OFF - signal absent").

However, when it comes to logical expressions and, especially, the truth table of logical elements, instead of the general concept of "signal presence" and "signal absence", bit values ​​are used, which represent the logic level "1" and the logic level "0", respectively.

Then four possible combinations of "A" and "B" for a 2-input logic element can be represented as follows:

  1. "OFF" - "OFF" or (0, 0)
  2. "OFF" - "ON" or (0, 1)
  3. "ON" - "OFF" or (1, 0)
  4. "ON" - "ON" or (1, 1)

Therefore, a logic circuit with three inputs will have eight possible combinations (2³) and so on. To ensure an easy understanding of the essence of the truth table, we will study it only on simple logic elements with the number of inputs not exceeding two. But, despite this, the principle of obtaining logical results for multi-input circuit elements remains the same.

In practice, the truth table consists of one column for each of the input variables (eg A and B), and one last column for all possible outcomes of the logical operation (Q). Therefore, each row of the truth table contains one of the possible input variables (for example, A = 1, B = 0), and the result of the operation with these values.

truth table

Element "And"

For the logical element "AND", the output Q will contain log.1 only if both inputs ("A" and "B") are given a signal log.1

Microcircuits containing the logical element "AND":

  • K155LI1, analogue of SN7408N
  • K155LI5 with open collector, similar to SN74451N
  • K555LI1, analogue of SN74LS08N
  • K555LI2 with open collector, similar to SN74LS09N

OR element

The output of Q, the “OR” element, will have a log.1 if any of the two inputs or both inputs are immediately logged.1


Microcircuits containing the logic element "OR":

  • K155LL1, analogue of SN7432N
  • K155LL2 with open collector, similar to SN75453N
  • K555LL1, analogue of SN74LS32N

Element "NOT"

In this case, the output of Q, the logical element "NOT", will have a signal opposite to the input signal.

Microcircuits containing a logical element "NOT":

  • K155LN1, similar to SN7404N
  • K155LN2 with open collector, similar to SN7405N
  • K155LN3, similar to SN7406N
  • K155LN5 with open collector, similar to SN7416N
  • K155LN6, analogue of SN7466N

Element "AND-NOT"

The output Q of the "AND-NOT" element will be log.1 if there is no log.1 signal at both inputs at the same time

Microcircuits containing a logical element "AND-NOT":

  • K155LA3, similar to SN7400N
  • K155LA8, similar to SN7401N
  • K155LA9 with open collector, similar to SN7403N
  • K155LA11 with open collector, similar to SN7426N
  • K155LA12 with open collector, similar to SN7437N
  • K155LA13 with open collector, similar to SN7438N
  • K155LA18 with open collector, similar to SN75452N

OR-NOT element

Only if we apply log.0 to both inputs of the OR-NOT logic element, we will get the corresponding log.1 signal at its output Q

Microcircuits containing the logical element "OR-NOT":

  • K155LE1, analogue of SN7402N
  • K155LE5, similar to SN7428N
  • K155LE6, similar to SN74128N

XOR element

In this case, the output Q will contain log.1 if two opposite signals are applied to the input of the XOR element.

Microcircuits containing the logical element "XOR":

  • K155LP5, similar to SN7486N

Let's summarize by collecting all the previously obtained results of the work of logical elements in a single truth table:

Any digital microcircuits are built on the basis of the simplest logic elements:

Consider the design and operation of digital logic elements in more detail.

inverter

The simplest logic element is the inverter, which simply changes the input signal to the exact opposite value. It is written in the following form:

where the line over the input value and denotes its change to the opposite. The same action can be written with the help given in table 1. Since the inverter has only one input, its truth table consists of only two lines.

Table 1. Inverter gate truth table

In Out
0 1
1 0

As a logical inverter, you can use the simplest amplifier with a transistor switched on (or a source for a field effect transistor). The schematic diagram of the inverter logic element, made on a bipolar n-p-n transistor, is shown in Figure 1.


Figure 1. Scheme of the simplest logical inverter

Logic inverter chips can have different signal propagation times and can operate on different types of loads. They can be performed on one or several transistors. The most common logic elements are made by TTL, ESL and CMOS technologies. But regardless of the logic element scheme and its parameters, they all perform the same function.

In order for the features of switching on transistors not to obscure the function performed, special designations for logical elements were introduced - conditional graphic designations. inverter is shown in Figure 2.


Figure 2. Conventional graphic designation of a logical inverter

Inverters are present in almost all series of digital microcircuits. In domestic microcircuits, inverters are designated by the letters LN. For example, the 1533LN1 chip contains 6 inverters. Foreign microcircuits to indicate the type of microcircuit, a digital designation is used. An example of an IC containing inverters is the 74ALS04. The name of the microcircuit reflects that it is compatible with TTL microcircuits (74), produced according to improved low-power Schottky technology (ALS), contains inverters (04).

Currently, surface-mounted microcircuits (SMD microcircuits) are more often used, which contain one logical element each, in particular an inverter. An example is the SN74LVC1G04 chip. The microcircuit is manufactured by Texas Instruments (SN), is compatible with TTL microcircuits (74) is produced according to low-voltage CMOS technology (LVC), contains only one logic element (1G), it is an inverter (04).

To study the inverting logic element, you can use widely available electronic elements. So, as an input signal generator, you can use ordinary switches or toggle switches. To study the truth table, you can even use a regular wire, which we will alternately connect to a power source or a common wire. As a logic probe, a low-voltage light bulb or LED connected in series with a current-limiting one can be used. A schematic diagram of the study of the logic element of the inverter, implemented using these simple electronic elements, is shown in Figure 3.


Figure 3. Logic Inverter Study Diagram

The scheme for studying a digital logic element, shown in Figure 3, allows you to visually obtain data for the truth table. A similar study is carried out in More complete characteristics of the digital inverter logic element, such as the delay time of the input signal, the rate of rise and fall of the signal edges at the output, can be obtained using a pulse generator and an oscilloscope (preferably a two-channel oscilloscope).

Logic element "AND"

The next simplest logical element is a circuit that implements the operation of logical multiplication "AND":

F(x 1 ,x 2) = x 1 ^x 2

where the symbol ^ and denotes the logical multiplication function. Sometimes the same function is written in a different form:

F(x 1 ,x 2) = x 1 ^x 2 = x 1 x 2 = x 1 &x 2 .

The same action can be written using the truth table shown in Table 2. The formula above uses two arguments. Therefore, the logic element that performs this function has two inputs. It is designated "2I". For the logical element "2I" the truth table will consist of four rows (2 2 = 4) .

Table 2. Truth table of the logical element "2I"

In1 In2 Out
0 0 0
0 1 0
1 0 0
1 1 1

As can be seen from the above truth table, an active signal at the output of this logic element appears only when there are ones at both the X and Y inputs. That is, this logical element actually implements the "AND" operation.

The easiest way to understand how the 2I logic element works is with a circuit built on idealized electronically controlled keys, as shown in Figure 2. In the above circuit diagram, current will flow only when both keys are closed, which means that a unit level at its output will appear only with two units at the input.


Figure 4. Schematic diagram of the logic element "2I"

The conditional-graphic representation of the circuit that performs the logical function "2I" on the circuit diagrams is shown in Figure 3, and from now on, the circuits that perform the "AND" function will be shown in this form. This image does not depend on the specific circuit diagram of the device that implements the logical multiplication function.


Figure 5. Conditionally-graphic image of the logical element "2I"

The function of the logical multiplication of three variables is described in the same way:

F(x 1 ,x 2 ,x 3)=x 1 ^x 2 ^x 3

Its truth table will already contain eight rows (2 3 = 4). The truth table of the three-input logical multiplication circuit "3I" is shown in Table 3, and the conditional graphic image is in Figure 4. In the circuit of the logical element "3I", built according to the principle of the circuit shown in Figure 2, you will have to add a third key.

Table 3. Truth table of the circuit that performs the logical function "3I"

In1 In2 In3 Out
0 0 0 0
0 0 1 0
0 1 0 0
0 1 1 0
1 0 0 0
1 0 1 0
1 1 0 0
1 1 1 1

You can get a similar truth table using the 3I logic element research circuit, similar to the logic inverter research circuit shown in Figure 3.


Figure 6. Conventional graphic designation of the circuit that performs the logical function "3I"

Logic element "OR"

The next simplest logical element is a circuit that implements the logical addition operation "OR":

F(x 1 ,x 2) = x 1 Vx 2

where the symbol V denotes the logical addition function. Sometimes the same function is written in a different form:

F(x 1 ,x 2) = x 1 Vx 2 = x 1 +x 2 = x 1 |x 2 .

The same action can be written using the truth table given in Table 4. The formula above uses two arguments. Therefore, the logic element that performs this function has two inputs. Such an element is designated "2OR". For the element "2OR" the truth table will consist of four rows (2 2 = 4).

Table 4. Truth table of the logic element "2OR"

In1 In2 Out
0 0 0
0 1 1
1 0 1
1 1 1

As in the case considered for , we will use the keys to implement the "2OR" scheme. This time we will connect the keys in parallel. The circuit that implements the truth table 4 is shown in Figure 5. As can be seen from the above circuit, the level of a logical unit will appear at its output as soon as any of the keys is closed, that is, the circuit implements the truth table shown in Table 4.


Figure 7. Schematic diagram of the logic element "2OR"

Since the function of logical summation can be implemented by various circuit diagrams, the special symbol "1" is used to designate this function on the circuit diagrams, as shown in Figure 6.


Figure 6. Conditionally-graphic image of a logical element that performs the "2OR" function

Date of the last update of the file 29.03.2018

Literature:

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